Ultrasonic sensors have been put to practical use in various kinds of apparatus including, for example, an ultrasonic-echo diagnostic apparatus for medical use and an ultrasonic flaw detector for nondestructive inspection.
As the ultrasonic sensors so far, those utilizing oscillation of a piezoelectric body have been mainly used. However, along with the recent progress of the MEMS technology, an ultrasonic sensor of capacitance-detection type using the MEMS technology has been developed.
In the ultrasonic sensor of capacitance-detection type, an oscillator having a cavity portion between mutually facing electrodes is formed on a semiconductor substrate, and when DC and AC voltages are applied and superimposed to the respective electrodes, a membrane oscillates in the vicinity of a resonant frequency, and ultrasonic waves are generated. By applying this principle and modifying the structure of the above-described electrodes, a 1.5 dimensional array of short-axis variable focus and a two dimensional array of real time 3D imaging have been researched and developed.
A technology concerning such an ultrasonic sensor is described in, for example, U.S. Pat. No. 6,320,239 B1 (Patent Document 1), in which a capacitance-detection type ultrasonic oscillator using a silicon substrate as a lower electrode is disclosed.
For example, U.S. Pat. No. 6,271,620B1 (Patent Document 2) and “IEEE ULTRASONICS SYMPOSIUM, (USA), 2003, p 577-p 580” (Non-patent Document 1) disclose a capacitance-detection type ultrasonic oscillator which is formed on a patterned lower electrode.
For example, U.S. Pat. No. 6,571,445B2 (Patent Document 3) and U.S. Pat. No. 6,562,650B2 (Patent Document 4) disclose a technology for forming a capacitance-detection type ultrasonic oscillator on an upper layer of a signal processing circuit formed on a silicon substrate.
For example, Japanese Patent Application Laid-Open Publication No. 5-6849 (Patent Document 5) and Japanese Patent Application Laid-Open Publication No. 2004-071767 (Patent Document 6) disclose a technology that, when an area larger than an area which can be exposed by single exposure is divided into a plurality of exposure areas and they are exposed in a reduced projection exposure process, the overlapping exposure is performed for the joint portions of the divided exposure areas. These Patent Documents 5 and 6 disclose the means for suppressing a fluctuation (shift) in a width of a resist pattern in the overlapping exposure portions from a desired dimension. However, they do not disclose the control of the resist pattern in a thickness direction in the overlapping exposure portions. This is because the resist pattern is sufficient if it has a film thickness enough to withstand the dry etching process and it is eliminated thereafter by ashing or the like and does not remain on a semiconductor chip.